Contact Information:

• Office Location: FH318
• Phone Number: (216) 687-2590
• Email: p.chu@csuohio.edu
• Personal Website: http://academic.csuohio.edu/chu_p/
• Schedule an appointment

Education:

• B.S., National Chiao - Tung University, Taiwan
• M.S., Computer Engineering - Iowa State University
• Ph.D., Computer Engineering - Iowa State University, 1989

Research Interests:

• Digital Systems
• Computer Architecture
• Computer Networks

Classes Frequently Taught

• EEC 382 Digital Systems and Lab
• EEC 487 Advanced Digital Systems
• EEC 488 Hardware-Software Co-design
• EEC 490 Senior Design
• EEC 580 Modern Digital Design
• ESC120 Computer Engineering

Recent Publications

• Pong P. Chu. 2012. Embedded SoPC Design with Nios II Processor and Verilog Examples (1st ed.). Wiley Publishing.
• Pong P. Chu. 2008. FPGA Prototyping Byverilog Examples. Wiley-Interscience, New York, NY, USA.
• Pong P. Chu. 2008. FPGA Prototyping by VHDL Examples: Xilinx Spartan-3 Version..
• Pong P. Chu. 2006. RTL Hardware Design Using VHDL: Coding for Efficiency, Portability, and Scalability. Wiley-IEEE Press.
• Pong P. Chu. 1996. A Reprogrammable FPGA-Based ATM Traffic Generator. In Proceedings of the 6th Great Lakes Symposium on VLSI (GLSVLSI '96). IEEE Computer Society, Washington, DC, USA, 35-.
• Pong P. Chu and Ramana Gottipati. 1994. Write Buffer Design for On-Chip Cache. In Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors (ICCS '94). IEEE Computer Society, Washington, DC, USA, 311-316.
• Pong P. Chu. 1994. Neural networks as a parallel processing paradigm: potential and problems. Neural, Parallel Sci. Comput. 2, 2 (June 1994), 205-224.