Cleveland State University

Department of Electrical and Computer Engineering

 

EEC 380

Digital Systems

Summer 2001

 

Description:    Binary number systems, Boolean algebra, combinational logic design principles and practices, sequential logic design principles and practices, memory elements, programmable logic devices (PLDs), logic families.

 

Objective:       After taking this course the student should be in a position to design a wide variety of digital systems using integrated circuits.  This course provides the necessary prerequisites for EEC 381, which is the digital systems laboratory.

 

Text:               J. Wakerly, Digital Design: Principles and Practices (Third Edition), Prentice Hall, 2000.

 

Prereqs:          EEC 313 - Electronics I

 

Time:              M W Th  4:00 - 5:28

 

Place:              Stilwell Hall Room 309

 

Instructor:      Dr. Dan Simon

                        Phone:  216-687-5407

                        Web:  http://academic.csuohio.edu/simond/

 

Grading:         Quizzes               25%

                        Midterm Exam     25%

                        Homework          20%

                        Final Exam          30%

 

Homework:     You can work with others on homework, but identical homework assignments will be given a grade of zero.  Homework will be accepted up to one class period late but a 10% deduction will be applied to late homework. Homework should be neat, pages should be stapled, and the problems should be in order. The homework assignments are given at  http://academic.csuohio.edu/simond/courses/eec380/homework.html.

 

Tests:              Quizzes and Exams will be closed-book and closed-notes.  No makeup quizzes or exams will be allowed without the prior permission of the instructor.

 

Course Outline

 

Week

Date

Topic

Text Chapters and Sections

1

May 21

Introduction, Number Systems

1; 2.1-6

2

May 28

Number Systems, Digital Logic

2.10-11,13; 3.1-2

3

June 4

Boolean Algebra, Combinational Ckts.

4.1-3

4

June 11

Combinational Ckts., PLDs, Decoders, Encoders

5.1-5

5

June 18

Three-State Devices, Multiplexers, Parity Ckts.

5.6-8

6

June 25

Comparators, Bistable Elements

5.9-10; 7.1

7

July 2

Latches, Flip-Flops, State Machines

7.2-3

8

July 9

State Machine Design

7.4-5

9

July 16

Commonly-Used Latches, Flip-Flops, PLDs

8.1-3

10

July 23

Commonly-Used Counters and Shift Registers

8.4-5

11

July 30

VACATION

None

12

August 6

Memory

10.1-3

 

Test Dates

 

Test

Date

Material

Quiz 1

June 6

Chapters 1-2

Quiz 2

June 20

Chapters 3-4

Quiz 3

June 27

Sections 5.1-5

Midterm Exam

July 9

Chapters 1-5

Quiz 4

July 18

Sections 7.1-3

Quiz 5

July 25

Sections 7.4-5

Quiz 6

August 8

Chapter 8

Final Exam

August 9

All

 

Grading Scale

 

93100

A

9092

A minus

8789

B plus

8386

B

8082

B minus

7779

C plus

7076

C

6069

D

 


Professor Simon's Home Page

Department of Electrical and Computer Engineering

Cleveland State University


Last Revised: May 18, 2001